1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a NAND flash memory device.
2. Discussion of Related Art
In semiconductor memory devices, redundant circuits are often used to improve production yield. In general, redundant circuits may be classified into row redundant circuits and column redundant circuits. The row redundant circuits include one or more rows of memory cells and related circuits required for activating redundant rows and defective rows of memory cells. Similarly, the column redundant circuit includes one or more columns of memory cells and a circuit required for activating redundant columns and deactivating defective columns of memory cells.
FIG. 1 is a block diagram schematically showing a conventional NAND flash memory device.
Referring to FIG. 1, a conventional NAND flash memory device includes a main field 10 and a redundant field 20. The main field 10 includes a memory cell array for storing main data, and a plurality of rows (or word lines) and a plurality of main columns (or main bit lines) arranged in the memory cell array. As widely known, a memory cell array of a NAND flash memory device has a NAND string structure. The redundant field 20 includes a redundancy memory cell array for replacing defective columns of the main field, and, as is obvious to one skilled in the art, the redundant memory cell array has the same structure as the main field 10. A main page buffer circuit 30 reads data stored in the main field 10 in a page unit during a read operation. A redundant page buffer circuit 40 reads data stored in the redundant field 20 during the read operation. Here, as is apparent to those having ordinary skill, the main field 10 and the redundant field 20 are configured to share the same row. In other words, when a row or page is selected, the main page buffer circuit 30 and the redundant page buffer circuit 40 read data from memory cells of the main and the redundant fields 10 and 20 connected to the selected row at the same time. The main page buffer circuit 30 and the redundant page buffer circuit 40 include page buffers which are widely known in this field.
Referring to FIG. 1, a column decoder circuit 50 generates column selection signals YSi in response to a column address YA, and a column gate circuit 60 generates main columns or main page buffers of the main field 10 in a predetermined unit such as a byte or a word in response to the column selection signals YSi. Main data bits MDm of the selected main rows or page buffers are transmitted to the multiplexer block 70. The redundant column gate circuit 80 is controlled by a redundancy control circuit 90, and selects at least one of the redundant columns of the redundant field 20 or the page buffers of the redundant page buffer circuit. The redundant data bits RDn (where n is 1 or an integer greater than 1) of the selected redundant columns or page buffers are transmitted to a multiplexer block 70.
The multiplexer block 70 receives the main and redundant data bits MDm and RDn which are output from the gate circuits 60 and 80, and outputs the main data bits MDm or the main and redundant data bits MDm and RDn in accordance with redundancy information from the redundant control circuit 90. For example, if all the main bits of the currently selected columns (or page buffers) are normal, the multiplexer block 70 outputs the main data bits MDm in accordance with the control of the redundancy control circuit 90. If one of the main data bits of the currently selected columns (or page buffers) is a defective data bit, the multiplexer block 70 outputs a redundancy data bit RDn together with other main data bits, instead of the defective main data bit in accordance with the redundancy information. The redundancy control circuit 90 is formed to store information of the addresses of the defective columns (or page buffers), and controls the redundancy column gate circuit 80 and the multiplexer block 70 in response to the input row address YA. It is apparent that the redundancy control circuit 90 is realized using a fuse box and a logic circuit widely known to those having ordinary skill in the art.
In the case of a NAND flash memory device as shown in FIG. 1, the time for transmitting the main data to the multiplexer block 70 is influenced by the column decoder circuit 50, while the time for transmitting the redundancy data to the multiplexer block 70 is influenced by the redundancy control circuit 90. In other words, the column gate circuit 60 and the redundancy column gate circuit 80 are controlled by different paths (a decoding path of a column decoder circuit and a decoding path of a redundancy control circuit). As a result, the time for outputting the main data is influenced by the redundancy gate circuit 80 controlled by the redundancy control circuit according to a column address.